Congratulations !!!

To :

Mohammad Izzat Mohammad Fadzil

Nur Ezani Ahmad Shukri

Nor Akmar Atan

Nurmalidyana Mohd Azami

May today's success be the beginning of tomorrow's achievements :)

Along with this message is my applause and gratitude for the wonderful job you've have done today and the days beforehand. 

Congratulations! I knew that if someone could do it, then it must be you.  Well done my friend!

Keep up the good work!

All done!!! - ezani

I have completed my task at Semyung University. I was explain about project phase one previously. Second phase(Synthesis) was successful done on  1st November 2011. This phase need my understanding to convert behavioral statement to verilog gate code.

behavioral statement code

behavioral test vector

verilog gate code

during  Synthesis Presentation

After that, I was proceed to phase 3(Layout) which is I need to design layout using Astro tools from verilog gate code. The task completed on 7th November 2011. 

layout chip for touch sensor chip

during layout presentation

On 8 November 2011, I was visited by Miss Suhaili Dinn and Miss Norhidayu Salimi for evaluation. I was present about my project, sub task and all activities conducted at Semyung University.

Miss Suhaili and us with Semyung University dean

during lecturer visit presentation

Thanks to UniKL MIIT that give me opportunities to join this program. To UniKL MIIT dean; Dr. Roslan Ismail, thanks because trust me in order to complete this program. To all UniKL lecturer, thanks for your support especially Madam Suriana, Madam Wida, Madam Ramona, Madam Robiah, Miss Suhaili and Miss Norhidayu..Not forget to En Megat and Madam Ozzi for your kindness.. 

I have one week free time to complete my INTRA report. Next week I will start mini project. :)

Till then..see you on the next entry..^_^

Nur Ezani~work progress~

PROJECT PROGRESS

As mention in my previous updated, my project tittle is Design Digital Logic For Touch Sensor Chip via Verilog. This project have four phase. Which is the due as below :

1. Phase One : 25 October 2011 

2. Phase Two : 1 November 2011

3. Phase Three : 7 November 2011

4. Phase Four : 15 November 2011

*date will change from time to time

PHASE 1

Preparation

Now, i'm in phase one. I have learnt how to create RTL(Register Transfer Level) and gate level (AND,OR & XOR).  To complete this phase, I need to do research and study about Full Adder (FA). Then, I need to understand how to create Top Chip (TC) and Bottom Chip (BC) via combining FA and AND gate.

                                           Bottom Chip                                           Top Chip

       Full Adder

Try to create TC.v and BC.v via Verilog

After successful create TC.v and BC.v, I need to create multiplier gate level code for 4x4 Multiplier and 8x8 Multiplier via Verilog.

This is 8x8 Multiplier

Create mul_8x8.v

To complete phase one, I need to conduct seminar on 25 October 2011. I was studied and prepared the slide  for my seminar.

My preparation slide and notes

Seminar

My Phase One seminar conducted on 25 October 2011. All my team mate was attend the seminar.

Seminar started!

During seminar

 With one of ITASIC team mate.

 SLIDE

Till then..see you on the next entry..^_^

Nor Akmar Binti Atan

I was assigned to Computer Department and placed directly under the dean of the department. Most of the time, I will sit in the lab with the tutor and other students. Right now they are working on a project that I’m not familiar with which is mostly involving LED and the new algorithms that they develop in to promote low power consumption and cost effective LED. For the time being I was not directly assigned to any part of their project. However, I was coached by one of the senior student here on java programming using tools that im new with; eclipse. 

My desk in the lab

Seminar

Right now I’ am working on a small project that involving sql database using mysql workbench. Beside, every week we are having 2 meeting with the dean on Monday and Friday evening. On Monday’s meeting we will be presenting about all of the things that we already study for that week. Especially about the project and task that we are assigned to. As for me I will have to present all the java skills and the output that I gain during the week. The Friday’s meeting was to discuss and present the latest new technology that existed out there. We have to prepare the presentation slide and explained technology in about 3 minutes per person. 
 

Java Code

sql workbench

Weekly/Daily Tasks:

• Attend Class
• JAVA Training
• Present newest technology
• Present weekly progress

As for classess im attending:

• Korean class(everyday from 9AM-11AM). 
• Introduction To Language (Every Tuesday 10.30-12.30)
• Korean Corporate Business Management(Every Wednesday 3.30-5.30)
• JSP Programming (Every Friday 2.30-4.30)

Monday's Seminar

Friday's Seminar

Here I communicate mostly in Korean and English. In my labs I will use Korean most of the times. I use English when I was with other international friends or the Korean friends that fluently speaks English. I was quite surprised when they can understand my Korean. I pick up all the sentences and the words from all the dramas and tv programs that I have been watching since I was a teenager. And frankly speaking, knowing some Korean language before coming here was a great help as they rarely and completely unfamiliar in using English with each other. However it is quite hard for me to talk formally and to write a formal form in Korean as I only pick up the conversations part. But, as I attend the Korean language class, I tried to build up some skills in writing and speaking. Recently i passed the 1st part test of Korean language with 82.5% marks. The passing mark is 70%. 

Studying Korean

By Yours Sincerely:

Nor Akmar Atan

BSE

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2011909025