Nur Ezani~work progress~

PROJECT PROGRESS

As mention in my previous updated, my project tittle is Design Digital Logic For Touch Sensor Chip via Verilog. This project have four phase. Which is the due as below :

1. Phase One : 25 October 2011 

2. Phase Two : 1 November 2011

3. Phase Three : 7 November 2011

4. Phase Four : 15 November 2011

*date will change from time to time

PHASE 1

Preparation

Now, i'm in phase one. I have learnt how to create RTL(Register Transfer Level) and gate level (AND,OR & XOR).  To complete this phase, I need to do research and study about Full Adder (FA). Then, I need to understand how to create Top Chip (TC) and Bottom Chip (BC) via combining FA and AND gate.

                                           Bottom Chip                                           Top Chip

       Full Adder

Try to create TC.v and BC.v via Verilog

After successful create TC.v and BC.v, I need to create multiplier gate level code for 4x4 Multiplier and 8x8 Multiplier via Verilog.

This is 8x8 Multiplier

Create mul_8x8.v

To complete phase one, I need to conduct seminar on 25 October 2011. I was studied and prepared the slide  for my seminar.

My preparation slide and notes

Seminar

My Phase One seminar conducted on 25 October 2011. All my team mate was attend the seminar.

Seminar started!

During seminar

 With one of ITASIC team mate.

 SLIDE

Till then..see you on the next entry..^_^