Congratulations !!!

To :

Mohammad Izzat Mohammad Fadzil

Nur Ezani Ahmad Shukri

Nor Akmar Atan

Nurmalidyana Mohd Azami

May today's success be the beginning of tomorrow's achievements :)

Along with this message is my applause and gratitude for the wonderful job you've have done today and the days beforehand. 

Congratulations! I knew that if someone could do it, then it must be you.  Well done my friend!

Keep up the good work!

All done!!! - ezani

I have completed my task at Semyung University. I was explain about project phase one previously. Second phase(Synthesis) was successful done on  1st November 2011. This phase need my understanding to convert behavioral statement to verilog gate code.

behavioral statement code

behavioral test vector

verilog gate code

during  Synthesis Presentation

After that, I was proceed to phase 3(Layout) which is I need to design layout using Astro tools from verilog gate code. The task completed on 7th November 2011. 

layout chip for touch sensor chip

during layout presentation

On 8 November 2011, I was visited by Miss Suhaili Dinn and Miss Norhidayu Salimi for evaluation. I was present about my project, sub task and all activities conducted at Semyung University.

Miss Suhaili and us with Semyung University dean

during lecturer visit presentation

Thanks to UniKL MIIT that give me opportunities to join this program. To UniKL MIIT dean; Dr. Roslan Ismail, thanks because trust me in order to complete this program. To all UniKL lecturer, thanks for your support especially Madam Suriana, Madam Wida, Madam Ramona, Madam Robiah, Miss Suhaili and Miss Norhidayu..Not forget to En Megat and Madam Ozzi for your kindness.. 

I have one week free time to complete my INTRA report. Next week I will start mini project. :)

Till then..see you on the next entry..^_^

Nur Ezani~work progress~

PROJECT PROGRESS

As mention in my previous updated, my project tittle is Design Digital Logic For Touch Sensor Chip via Verilog. This project have four phase. Which is the due as below :

1. Phase One : 25 October 2011 

2. Phase Two : 1 November 2011

3. Phase Three : 7 November 2011

4. Phase Four : 15 November 2011

*date will change from time to time

PHASE 1

Preparation

Now, i'm in phase one. I have learnt how to create RTL(Register Transfer Level) and gate level (AND,OR & XOR).  To complete this phase, I need to do research and study about Full Adder (FA). Then, I need to understand how to create Top Chip (TC) and Bottom Chip (BC) via combining FA and AND gate.

                                           Bottom Chip                                           Top Chip

       Full Adder

Try to create TC.v and BC.v via Verilog

After successful create TC.v and BC.v, I need to create multiplier gate level code for 4x4 Multiplier and 8x8 Multiplier via Verilog.

This is 8x8 Multiplier

Create mul_8x8.v

To complete phase one, I need to conduct seminar on 25 October 2011. I was studied and prepared the slide  for my seminar.

My preparation slide and notes

Seminar

My Phase One seminar conducted on 25 October 2011. All my team mate was attend the seminar.

Seminar started!

During seminar

 With one of ITASIC team mate.

 SLIDE

Till then..see you on the next entry..^_^